-- Copyright (c) 2010, Pavel Kovar
-- All rights reserved.
--
---------------------------------------------------------------------------------------
-- This file is a part of the Witch Navigator project

-- 6x Universal correlators
-- Implemented
--   * Building blocks interconnection


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity cor6 is
    Generic (
                prn_length : integer := 10230
            );
    Port ( sr_in : in  STD_LOGIC_VECTOR (7 downto 0);
           si_in : in  STD_LOGIC_VECTOR (7 downto 0);
           clk_dsp : in  STD_LOGIC;
           b_code : IN std_logic_vector(31 downto 0);
           b_phase : IN std_logic_vector(31 downto 0);
           cor_space : IN std_logic_vector(2 downto 0);
           phase : in STD_LOGIC_VECTOR (2 downto 0);
           nco_code_out : OUT std_logic_vector(31 downto 0);
           nco_phase_out : OUT std_logic_vector(31 downto 0);
           acc_e_out : OUT std_logic_vector(31 downto 0);
           acc_l_out : OUT std_logic_vector(31 downto 0);
           prn_tic_e : OUT std_logic;
           prn_tic_l : OUT std_logic;
           clk_ctr : IN std_logic;
           prn_mem_we : IN std_logic_vector(3 downto 0);
           prn_mem_addr : IN std_logic_vector(11 downto 0);
           prn_mem_in : IN std_logic_vector(31 downto 0)
       );
end cor6;

architecture Behavioral of cor6 is

signal sin_out, cos_out: std_logic_vector(7 downto 0);
signal prn_tic_e_pom, prn_tic_l_pom: std_logic;
signal prn_e_pom, prn_l_pom: std_logic;

	COMPONENT nco_code
	GENERIC (
	   prn_length : integer
		);
	PORT(
		b_code : IN std_logic_vector(31 downto 0);
		phase : IN std_logic_vector(2 downto 0);
		clk_dsp : IN std_logic;
		cor_space : IN std_logic_vector(2 downto 0);
		clk_ctr : IN std_logic;
		mem_we : IN std_logic_vector(3 downto 0);
		mem_addr : IN std_logic_vector(11 downto 0);
		mem_in : IN std_logic_vector(31 downto 0);          
		prn_e : OUT std_logic;
		prn_l : OUT std_logic;
		prn_tic_e : OUT std_logic;
		prn_tic_l : OUT std_logic;
		nco_code_out : OUT std_logic_vector(31 downto 0)
		);
	END COMPONENT;

	COMPONENT nco_phase
	PORT(
		b_phase : IN std_logic_vector(31 downto 0);
		clk_dsp : IN std_logic;          
		sin_out : OUT std_logic_vector(7 downto 0);
		cos_out : OUT std_logic_vector(7 downto 0);
		nco_phase_out : OUT std_logic_vector(31 downto 0)
		);
	END COMPONENT;

	COMPONENT cor_mac
	PORT(
		clk_dsp : IN std_logic;
		cos_in : IN std_logic_vector(7 downto 0);
		sin_in : IN std_logic_vector(7 downto 0);
		sig_real : IN std_logic_vector(7 downto 0);
		sig_imag : IN std_logic_vector(7 downto 0);
		prn_e : IN std_logic;
		prn_l : IN std_logic;
		tic_e : IN std_logic;
		tic_l : IN std_logic;          
		cor_e_out : OUT std_logic_vector(31 downto 0);
		cor_l_out : OUT std_logic_vector(31 downto 0)
		);
	END COMPONENT;
	
begin

prn_tic_e <= prn_tic_e_pom;
prn_tic_l <= prn_tic_l_pom;

	nco_c: nco_code
	GENERIC MAP(
		prn_length => prn_length		
	)
	PORT MAP(
		b_code => b_code,
		phase => phase,
		clk_dsp => clk_dsp,
		cor_space => cor_space,
		prn_e => prn_e_pom,
		prn_l => prn_l_pom,
		prn_tic_e => prn_tic_e_pom,
		prn_tic_l => prn_tic_l_pom,
		nco_code_out => nco_code_out,
		clk_ctr => clk_ctr,
		mem_we => prn_mem_we,
		mem_addr => prn_mem_addr,
		mem_in => prn_mem_in
	);

	nco_p: nco_phase PORT MAP(
		b_phase => b_phase,
		clk_dsp => clk_dsp,
		sin_out => sin_out,
		cos_out => cos_out,
		nco_phase_out => nco_phase_out
	);

	c_mac: cor_mac PORT MAP(
		clk_dsp => clk_dsp,
		cos_in => cos_out,
		sin_in => sin_out,
		sig_real => sr_in,
		sig_imag => si_in,
		prn_e => prn_e_pom,
		prn_l => prn_l_pom,
		tic_e => prn_tic_e_pom,
		tic_l => prn_tic_l_pom,
		cor_e_out => acc_e_out,
		cor_l_out => acc_l_out
	);

end Behavioral;

